1. Field of the Invention
The present invention generally relates to a testing substrate and a testing method thereof, and more particularly to a testing substrate for fine pitch wafer level tests and a testing method thereof.
2. Description of Prior Art
With rapid development of integration of integrated circuit (IC) technologies, relevant package technologies have reached an unprecedented and innovative level than ever. In numerous innovative package technologies, a wafer level package (WLP) or a chip scale package (CSP) is a type of IC chip package and is also the most representative skill which is considered as a revolutionary skill. After the wafer level packages, the sizes of IC chips are almost the same as original sizes of dies. Therefore, it is also well known as a wafer level chip scale package (WLCSP) in industry. Regardless of the WLP which is packaged on the wafer or packages of other forms, numbers of solder balls and bumps of one IC chip to be tested is increasing and sizes are small. Distances among the soldering balls and the bumps are decreased (fine pitch) for meeting design trends of miniaturization of electronic products. Current probing technologies utilized in the wafer level comprise cantilever probe cards and vertical probe cards. In order to match with the increasing numbers of the solder balls and the bumps, the small sizes and the fine pitch requirements, a number of probes is required to be increased and probe spacing between the probes should be decreased. Material of the probes comprises tungsten (W), beryllium copper (BeCu), palladium alloy and so on. Regardless of the probe cards are the cantilever probe cards or the vertical probe cards, the probing technologies faces difficulties and disadvantages due to the small sizes of the soldering balls and the bumps.
Firstly, in the probing technologies, the probes have to destroy oxidation layers on the soldering balls and the bumps for forming probe marks on surfaces of pads, thereby achieving a requirement of contact resistance in electrical tests. However, it is difficult not to destroy structures of the soldering balls and the bumps. The probe marks must occur for ensuing that the probes of one probe card contact the pads. Furthermore, it can be understood by observing the probe marks that when the probe marks are small, the electrical tests fail due to poor contact. When the probe marks are large, the surfaces of the pads are destroyed and gaps are formed in bonding surfaces, such that poor bonding occurs in the following bonding processes. Even more seriously, oxidation is formed after the surfaces of the pads are destroyed, and thus the bonding surfaces are oxidized and bonding strength is decreased.
Accordingly, although the material and the structure of the probes are improved in the current industry, this is a basic and main subject in the semiconductor testing industry. When the soldering balls and the bumps are getting smaller and smaller, a rate of destroying portion is increased. In order to ensure a yield rate after the electrical tests, additional optical inspection machines and processes are required for examining the tested products. As a result, burden and cost are increased.
Furthermore, the soldering balls and the bumps are not similar to the pads which are flat. After miniaturization, the structures do not have enough flat surfaces. It is impossible to test the soldering balls and the bumps by the probes. Accordingly, it is necessary to develop a testing device and a testing method thereof for a wafer level and fine-pitch test.